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CD4724BC 8-Bit Addressable Latch
October 1987 Revised January 1999
CD4724BC 8-Bit Addressable Latch
General Description
The CD4724BC is an 8-bit addressable latch with three address inputs (A0-A2), an active low enable input (E), active high clear input (CL), a data input (D) and eight outputs (Q0-Q7). Data is entered into a particular bit in the latch when that is addressed by the address inputs and the enable (E) is LOW. Data entry is inhibited when enable (E) is HIGH. When clear (CL) and enable (E) are HIGH, all outputs are LOW. When clear (CL) is HIGH and enable (E) is LOW, the channel demultiplexing occurs. The bit that is addressed has an active output which follows the data input while all unaddressed bits are held LOW. When operating in the addressable latch mode (E = CL = LOW), changing more than one bit of the address could impose a transient wrong address. Therefore, this should only be done while in the memory mode (E = HIGH, CL = LOW).
Features
s Wide supply voltage range: s High noise immunity: s Low power TTL compatibility: fan out of 2 driving 74L or 1 driving 74LS s Serial to parallel capability s Storage register capability s Random (addressable) data entry s Active high demultiplexing capability s Common active high clear 3.0V to 15V 0.45 VDD (typ.)
Ordering Code:
Order Number CD4724BCM CD4724BCN Package Number M16A N16E Package Description 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow Body 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter "X" to the ordering code.
Connection Diagram
Pin Assignments for DIP and SOIC
Truth Table
Mode Selection E CL Addressed Latch L H L H L L Follows Data Unaddressed Latch Holds Previous Data Addressable Latch Memory Demultiplexer Clear Mode
Hold Previous Holds Previous Data Data Reset to "0" Reset to "0"
H Follows Data H Reset to "0"
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(c) 1999 Fairchild Semiconductor Corporation
DS006003.prf
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CD4724BC
Logic Diagram
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CD4724BC
Absolute Maximum Ratings(Note 1)
(Note 2) DC Supply Voltage (VDD ) Input Voltage (VIN) Storage Temperature (TS) Power Dissipation (PD) Dual-In-Line Small Outline Lead Temperature (TL) (Soldering, 10 seconds) 260C (Note 2) 700 mW 500 mW -0.5V to +18 VDC -0.5V to VDD +0.5 VDC -65C to +150C
Recommended Operating Conditions (Note 2)
DC Supply Voltage (VDD) Input Voltage (VIN) Operating Temperature Range (TA) 3.0V to 15 VDC 0V to VDD VDC -40C to +85C
Note 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed; they are not meant to imply that the devices should be operated at these limits. The tables of "Recommended Operating Conditions" and Electrical Characteristics" provide conditions for actual device operation. Note 2: VSS = 0V unless otherwise specified.
DC Electrical Characteristics
Symbol IDD Parameter Quiescent Device Current VOL LOW Level Output Voltage VDD = 5V VDD = 10V VDD = 15V |IO| 1 A VDD = 5V VDD = 10V VDD = 15V VOH HIGH Level Output Voltage |IO| 1 A VDD = 5V VDD = 10V VDD = 15V VIL LOW Level Input Voltage VIH HIGH Level Input Voltage IOL LOW Level Output Current (Note 3) IOH HIGH Level Output Current (Note 3) IIN Input Current
Conditions
-40C Min Max 20 40 80 0.05 0.05 0.05 4.95 9.95 14.95 1.5 3.0 4.0 3.5 7.0 11.0 0.52 1.3 3.6 -0.52 -1.3 -3.6 -0.30 0.30 3.5 7.0 11.0 0.44 1.1 3.0 -0.44 -1.1 -3.0 4.95 9.95 14.95 Min
+25C Typ 0.02 0.02 0.02 0 0 0 5.0 10 15 2.25 4.5 6.75 2.75 5.5 8.25 0.88 2.25 8.8 -0.88 -2.25 -8.8 -10-5 10-5 -0.30 0.30 1.5 3.0 4.0 Max 20 40 80 0.05 0.05 0.05
+85C Min Max 150 300 600 0.05 0.05 0.05 4.95 9.95 14.95 1.5 3.0 4.0 3.5 7.0 11.0 0.36 0.9 2.4 -0.36 -0.9 -2.4 -1.0 1.0
Units A A A V V V V V V V V V V V V mA mA mA mA mA mA A A
VDD = 5V, VO = 0.5V or 4.5V VDD = 10V, VO = 1V or 9V VDD = 15V, VO = 1.5V or 13.5V VDD = 5V, VO = 0.5V or 4.5V VDD = 10V, VO = 1V or 9V VDD = 15V, VO = 1.5V or 13.5V VDD = 5V, VO = 0.4V VDD = 10V, VO = 0.5V VDD = 15V, VO = 1.5V VDD = 5V, VO = 4.6V VDD = 10V, VO = 9.5V VDD = 15V, VO = 13.5V VDD = 15V, VIN = 0V VDD = 15V, VIN = 15V
Note 3: IOL and IOH are tested one output at a time.
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CD4724BC
AC Electrical Characteristics
Symbol tPHL, tPLH Parameter Propagation Delay Data to Output tPLH, tPHL Propagation Delay Enable to Output tPHL Propagation Delay Clear to Output tPLH, tPHL Propagation Delay Address to Output tTHL, tTLH Transition Time (Any Output) TWH, TWL Minimum Data Pulse Width tWH, tWL Minimum Address Pulse Width tWH Minimum Clear Pulse Width tSU Minimum Setup Time Data to E tH Minimum Hold Time Data to E tSU Minimum Setup Time Address to E tH Minimum Hold Time Address to E CPD CIN Power Dissipation Capacitance Input Capacitance
(Note 4)
Conditions Min Typ 200 75 50 200 80 60 175 80 65 225 100 75 100 50 40 100 50 40 200 100 65 75 40 25 40 20 15 60 30 25 -15 0 0 -50 -20 -15 100 5.0 7.5 Max 400 150 100 400 160 120 350 160 130 450 200 150 200 100 80 200 100 80 400 200 125 150 75 50 80 40 30 120 60 50 50 30 20 15 10 5 Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns pF pF
TA = 25C, CL = 50 pF, RL = 200k, Input tr = tf = 20 ns, unless otherwise noted VDD = 5V VDD = 10V VDD = 15V VDD = 5V VDD = 10V VDD = 15V VDD = 5V VDD = 10V VDD = 15V VDD = 5V VDD = 10V VDD = 15V VDD = 5V VDD = 10V VDD = 15V VDD = 5V VDD = 10V VDD = 15V VDD = 5V VDD = 10V VDD = 15V VDD = 5V VDD = 10V VDD = 15V VDD = 5V VDD = 10V VDD = 15V VDD = 5V VDD = 10V VDD = 15V VDD = 5V VDD = 10V VDD = 15V VDD = 5V VDD = 10V VDD = 15V Per Package (Note 5) Any Input
Note 4: AC Parameters are guaranteed by DC correlated testing. Note 5: Dynamic power dissipation (PD) is given by: PD = (CPD + CL) VCC2f + PQ; where CL = load capacitance; f = frequency of operation; for further details, see Application Note AN-90, "Family Characteristics".
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CD4724BC
Switching Time Waveforms
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CD4724BC
Physical Dimensions inches (millimeters) unless otherwise noted
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow Body Package Number M16A
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CD4724BC 8-Bit Addressable Latch
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Package Number N16E
LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support 1. Life support devices or systems are devices or systems device or system whose failure to perform can be reawhich, (a) are intended for surgical implant into the sonably expected to cause the failure of the life support body, or (b) support or sustain life, and (c) whose failure device or system, or to affect its safety or effectiveness. to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the www.fairchildsemi.com user.
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.

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